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slos429 ? may 2004 features designed for wireless or cellular handsets and pdas 1.7 w into 8 ? from a 5-v supply at thd = 10% (typ) low supply current: 4 ma typ at 5 v shutdown current: 0.01 a typ fast startup with minimal pop only three external components ? improved psrr (?80 db) and wide supply voltage (2.5 v to 5.5 v) for direct battery operation ? fully differential design reduces rf rectification ? ?63 db cmrr eliminates two input coupling capacitors pin to pin compatible with tpa2005d1 and tpa6211a1 in qfn package available in 3 mm x 3 mm qfn package (drb) applications ideal for wireless handsets pdas notebook computers description the tpa6204a1 is a 1.7-w mono fully-differential amplifier designed to drive a speaker with at least 8- ? impedance while consuming only 20 mm 2 total printed-circuit board (pcb) area in most applications. the device operates from 2.5 v to 5.5 v, drawing only 4 ma of quiescent supply current. the tpa6204a1 is available in the space-saving 3 mm x 3 mm qfn (drb) package. the tpa6204a1 is ideal for pda/smart phone applications due to features such as ?80-db supply voltage rejection from 20 hz to 2 khz, improved rf rectification immunity, small pcb area, and a fast startup with minimal pop. application circuit _ + v dd v o+ v o? gnd 6 5 8 7 to battery c s bias circuitry in? in+ 4 3 2 + ? in from dac shutdown r i r i 1 c (bypass) (1) 100 k ? 40 k ? 40 k ? 8 shutdown bypass in+ in? v o? gnd v dd v o+ 8-pin qfn (drb) package (top view) 7 6 5 1 2 3 4 (1) c (bypass) is optional. dgn package (top view) 1 2 3 4 8 7 6 5 shutdown bypass in+ in? v o? gnd v dd v o+ please be aware that an important notice concerning availability , standard warranty, and use in critical applications of t exas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. www.ti.com copyright ? 2004, texas instruments incorporated
slos429 ? may 2004 www.ti.com 2 these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam duri ng storage or handling to prevent electrostatic damage to the mos gates. ordering information packaged device qfn (drb) msop (dgn) device tpa6204a1drb TPA6204A1DGN symbolization ayj tbd (1) the drb is only available taped and reeled. to order taped and reeled parts, add the suffix r to the part number (tp a6204a1drbr). terminal functions terminal i/o description name drb i/o description in? 4 i negative dif ferential input in+ 3 i positive dif ferential input v dd 6 i power supply v o+ 5 o positive btl output gnd 7 i high-current ground v o? 8 o negative btl output shutdown 1 i shutdown terminal (active low logic) bypass 2 mid-supply voltage, adding a bypass capacitor improves psrr thermal pad ? ? connect to ground. thermal pad must be soldered down in all applications to properly secure device on the pcb. absolute maximum ratings over oper ating free-air temperature range unless otherwise noted (1) unit supply voltage, v dd ?0.3 v to 6 v input voltage, v i ?0.3 v to v dd + 0.3 v continuous total power dissipation see dissipatio n rating table operating free-air temperature, t a ?40 c to 85 c junction temperature, t j ?40 c to 150 c storage temperature, t stg ?65 c to 85 c lead temperature 1,6 mm (1/16 inch) from case for 10 seconds drb 260 c (1) stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. package dissipation ratings package t a 25 c derating factor (1) t a = 70 c t a = 85 c package t a 25 c power rating derating factor (1) t a = 70 c power rating t a = 85 c power rating drb 2.7 w 21.8 mw/ c 1.7 w 1.4 w (1)) derating factor based on high-k board layout. recommended operating conditions min typ max unit supply voltage, v dd 2.5 5.5 v high-level input voltage, v ih shutdown 1.55 v low-level input voltage, v il shutdown 0.5 v operating free-air temperature, t a ?40 85 c
slos429 ? may 2004 www.ti.com 3 electrical characteristics, t a = 25 c parameter test conditions min typ max unit v os output offset voltage (measured differentially) v i = 0 v differential, gain = 1 v/v, v dd = 5.5 v ?9 0.3 9 mv psrr power supply rejection ratio v dd = 2.5 v to 5.5 v ?85 ?60 db v ic common mode input range v dd = 2.5 v to 5.5 v 0.5 v dd ?0.8 v cmrr common mode rejection ratio v dd = 5.5 v, v ic = 0.5 v to 4.7 v ?63 ?40 db cmrr common mode rejection ratio v dd = 2.5 v, v ic = 0.5 v to 1.7 v ?63 ?40 db r l = 8 ? , gain = 1 v/v, v dd = 5.5 v 0.45 low-output swing r l = 8 ? , v in+ = v dd , v = 0 v, gain = 1 v/v, v in? = 0 v or v = v v dd = 3.6 v 0.37 v low-output swing v in+ = v dd , v in+ = 0 v, v in? = 0 v or v in? = v dd v dd = 2.5 v 0.26 0.4 v r l = 8 ? , gain = 1 v/v, v dd = 5.5 v 4.95 high-output swing r l = 8 ? , v in+ = v dd , v = v gain = 1 v/v, v in? = 0 v or v = 0 v v dd = 3.6 v 3.18 v high-output swing v in+ = v dd , v in? = v dd v in? = 0 v or v in+ = 0 v v dd = 2.5 v 2 2.13 v | i ih | high-level input current, shut- down v dd = 5.5 v, v i = 5.8 v 58 100 a | i il | low-level input current, shut- down v dd = 5.5 v, v i = ?0.3 v 3 100 a i q quiescent current v dd = 2.5 v to 5.5 v, no load 4 6 ma i (sd) supply current v(shutdown ) 0.5 v, v dd = 2.5 v to 5.5 v, r l = 8 ? 0.01 1 a gain r l = 8 ? 38 k ? r i 40 k ? r i 42 k ? r i v/v resistance from shutdown to gnd 100 k ? operating characteristics, t a = 25 c, gain = 1 v/v parameter test conditions min typ max unit thd + n= 1%, f = 1 khz, v dd = 5 v 1.36 thd + n= 1%, f = 1 khz, r l = 8 ? = 8 v dd = 2.5 v 0.33 w p o output power thd + n= 10%, f = 1 khz, v dd = 5 v 1.7 thd + n= 10%, f = 1 khz , r l = 8 ? = 8 v dd = 2.5 v 0.4 w v dd = 5 v, p o = 1 w, r l = 8 ?, f = 1 khz 0.02% thd+n total harmonic distortion plus noise v dd = 3.6 v, p o = 0.5 w, r l = 8 ?, f = 1 khz 0.02% thd+n total harmonic distortion plus noise v dd = 2.5 v, p o = 200 mw, r l = 8 ?, f = 1 khz 0.03% k svr supply ripple rejection ratio v dd = 3.6 v, inputs ac-grounded f = 217 hz ?80 db k svr supply ripple rejection ratio inputs ac-grounded with c i = 2 f, v (ripple) = 200 mv pp f = 20 hz to 20 khz ?70 db snr signal-to-noise ratio v dd = 5 v, p o = 1 w, r l = 8 ? 105 db v n output voltage noise v dd = 3.6 v, f = 20 hz to 20 khz, no weighting 15 v rms v n output voltage noise f = 20 hz to 20 khz, inputs ac-grounded with c i = 2 f a weighting 12 v rms cmrr common mode rejection ratio v dd = 3.6 v v ic = 1 v pp f = 217 hz ?65 db r f feedback resistance 38 40 44 k ? start-up time from shutdown v dd = 3.6 v, c bypass = 0.1 f 27 ms
slos429 ? may 2004 www.ti.com 4 typical characteristics table of graphs figure p o output power vs supply voltage 1 p o output power vs load resistance 2 p d power dissipation vs output power 3 vs output power 4 thd+n total harmonic distortion + noise vs frequency 5 thd+n total harmonic distortion + noise vs common-mode input voltage 6 k svr supply voltage rejection ratio vs frequency 7 gsm power supply rejection vs time 8 gsm power supply rejection vs frequency 9 closed loop gain/phase vs frequency 10 open loop gain/phase vs frequency 11 i dd supply current vs supply voltage 12 i dd supply current vs shutdown voltage 13 start-up time vs bypass capacitor 14 figure 1 0 0.5 1 1.5 2 2.5 3 3.5 2.5 3 3.5 4 4.5 5 v dd ? supply voltage ? v ? output power ? w output power vs supply voltage p o f = 1 khz gain = 1 v/v p o = 8 ? , thd 1% p o = 8 ? , thd 10% figure 2 r l ? load resistance ? ? output power vs load resistance ? output power ? w p o 0 0.5 1 1.5 2 2.5 3 3.5 813 182328 v dd = 5 v, thd 1% v dd = 2.5 v, thd 10% v dd = 2.5 v, thd 1% v dd = 5 v, thd 10% v dd = 3.6 v, thd 10% v dd = 3.6 v, thd 1% f = 1 khz gain = 1 v/v
slos429 ? may 2004 www.ti.com 5 figure 3 0 0.2 0.4 0.6 0.8 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 power dissipation vs output power ? power dissipation ? w p d p o ? output power ? w 5 v 3.6 v 8 figure 4 0.04 0.044 0.048 0.052 0.056 0.06 012345 f = 1 khz p o = 200 mw, r l = 1 khz v ic ? common mode input voltage ? v total harmonic distortion + noise vs common mode input voltage thd+n ? total harmonic distortion + noise ? % v dd = 3.6 v v dd = 5 v v dd = 2.5 v figure 5 0.01 20 0.02 0.05 0.1 0.2 0.5 1 2 5 10 10m 20m 50m 100m 200m 500m 1 2 p o ? output power ? w total harmonic distortion + noise vs output power thd+n ? total harmonic distortion + noise ? % 2.5 v 3.6 v 5 v r l = 8 ? , c (bypass) = 0 to 1 f, gain = 1 v/v f = 1khz figure 6 0.001 10 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 20 20k 50 100 200 500 1k 2k 5k 10k f ? frequency ? hz total harmonic distortion + noise vs frequency thd+n ? total harmonic distortion + noise ? % 0.1 w 0.6 w 0.25 w v dd = 3.6 v, r l = 8 ? , , c (bypass) = 0 to 1 f, gain = 1 v/v, c i = 2 f
slos429 ? may 2004 www.ti.com 6 figure 7 f ? frequency ? hz +0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 20 20k 50 100 200 500 1k 2k 5k 10k supply voltage rejection ratio vs frequency k svr ? supply voltage rejection ratio ? db v dd = 3.6 v v dd = 2.5 v v dd = 5 v r l = 8 ? , c (bypass) = 0.47 f, gain = 1 v/v, c i = 2 f, inputs ac grounded figure 8 ?180 ?160 ?140 ?120 ?100 0 400 800 1200 1600 2000 ?150 ?100 ?50 0 f ? frequency ? hz ? supply voltage ? dbv v dd v dd shown in figure 9, r l = 8 ? , c i = 2.2 f, inputs grounded gsm power supply rejection vs frequency ? output voltage ? dbv v o c (bypass) = 0.47 f figure 9 c1 frequency 217 hz c1 ? duty 20% c1 pk?pk 500 mv ch1 100 mv/div ch4 10 mv/div 2 ms/div v dd v out voltage ? v t ? time ? ms gsm power supply rejection vs time r l = 8 ? c i = 2.2 f c (bypass) = 0.47 f 0 50 100 150 200 250 300 0 0.2 0.4 0.6 0.8 1 c (bypass) ? bypass capacitor ? f start-up t ime ? ms start-up time vs bypass capacitor figure 10
slos429 ? may 2004 www.ti.com 7 figure 11 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 ?180 ?150 ?120 ?90 ?60 ?30 0 30 60 90 120 150 180 1 100 10 k 100 k 1 m 10 m 1 k f ? frequency ? hz gain ? db phase ? degrees gain phase v dd = 5 v r l = 8 ? gain = 1 closed loop gain/phase vs frequency 10 figure 12 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 ?180 ?150 ?120 ?90 ?60 ?30 0 30 60 90 120 150 180 v dd = 5 v, r l = 8 ? gain phase 100 1 k 10 k 100 k 1 m f ? frequency ? hz open loop gain/phase vs frequency phase ? degrees gain ? db figure 13 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 t a = 25 c t a = ?40 c t a = 125 c v dd = 5 v v dd ? supply voltage ? v supply current vs supply voltage i dd ? supply current ? ma 0.00001 0.0001 0.001 0.01 0.1 1 10 0 1 2345 v dd = 3.6 v v dd = 5 v v dd = 2.5 v voltage on shutdown terminal ? v supply current vs shutdown voltage i dd ? supply current ? ma figure 14
slos429 ? may 2004 www.ti.com 8 application information fully differential amplifier the tpa6204a1 is a fully differential amplifier with differential inputs and outputs. the fully differential amplifier consists of a dif ferential amplifier and a common- mode amplifier. the differential amplifier ensures that the amplifier outputs a differential voltage that is equal to the differential input times the gain. the common-mode feedback ensures that the common-mode voltage at the output is biased around v dd /2 regardless of the common- mode voltage at the input. advantages of fully differential amplifiers input coupling capacitors not required: a fully differential amplifier with good cmrr, like the tpa6204a1, allows the inputs to be biased at voltage other than mid-supply. for example, if a dac has mid-supply lower than the mid-supply of the tpa6204a1, the common-mode feedback circuit adjusts for that, and the tpa6204a1 outputs are still biased at mid-supply of the tp a6204a1. the inputs of the tpa6204a1 can be biased from 0.5 v to v dd ? 0.8 v. if the inputs are biased outside of that range, input coupling capacitors are required. mid-supply bypass capacitor, c (bypass) , not required: the fully differential amplifier does not require a bypass capacitor. this is because any shift in the mid- supply affects both positive and negative channels equally and cancels at the differential output. however, removing the bypass capacitor slightly worsens power supply rejection ratio (k svr ), but a slight decrease of k svr may be acceptable when an additional component can be eliminated. better rf-immunity: gsm handsets save power by turning on and shutting off the rf transmitter at a rate of 217 hz. the transmitted signal is picked-up on input and output traces. the fully differential amplifier cancels the signal much better than the typical audio amplifier. application schematics figure 15 through figure 17 show application schematics for differential and single-ended inputs. typical values are shown in table 1. table 1. typical component values component value r i 40 k ? c (bypass) (1) 0.22 f c s 1 f c i 0.22 f (1) c (bypass) is optional _ + v dd v o+ v o? gnd 6 5 8 7 to battery c s bias circuitry in? in+ 4 3 2 + ? in from dac shutdown r i r i 1 c (bypass) (1) 100 k ? 40 k ? 40 k ? (1) c (bypass) is optional figure 15. typical differential input application schematic
slos429 ? may 2004 www.ti.com 9 _ + v dd v o+ v o? gnd 6 5 8 7 to battery c s bias circuitry in? in+ 4 3 2 shutdown r i r i 1 100 k ? 40 k ? 40 k ? + ? c i c i c (bypass) (1) (1) c (bypass) is optional figure 16. differential input application schematic optimized with input capacitors in c i c i _ + v dd v o+ v o? gnd 6 5 8 7 to battery c s bias circuitry in? in+ 4 3 2 shutdown r i r i 1 100 k ? 40 k ? 40 k ? c (bypass) (1) (1) c (bypass) is optional (2) due to the fully differential design of this amplifier, the performance is severly degraded if you connect the unused input to bypass when using single-ended inputs. figure 17. single-ended input application schematic
slos429 ? may 2004 www.ti.com 10 selecting components resistors (r i ) the input resistor (r i ) can be selected to set the gain of the amplifier according to equation 1. gain = r f /r i the internal feedback resistors (r f ) are trimmed to 40 k ? . resistor matching is very important in fully differential amplifiers. the balance of the output on the reference voltage depends on matched ratios of the resistors. cmrr, psrr, and the cancellation of the second harmonic distortion diminishes if resistor mismatch occurs. therefore, it is recommended to use 1% tolerance resistors or better to keep the performance optimized. using low-esr capacitors low-esr capacitors are recommended throughout this applications section. a real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. the voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. the lower the equivalent value of this resistance the more the real capacitor behaves like an ideal capacitor. bypass capacitor (c bypass ) and start-up time the internal voltage divider at the bypass pin of this device sets a mid-supply voltage for internal references and sets the output common mode voltage to v dd /2. adding a capacitor to this pin filters any noise into this pin and increases k svr . c (bypass) also determines the rise time of v o+ and v o? when the device is taken out of shutdown. the larger the capacitor, the slower the rise time. no tagno tagno tagno tagno tag show the relationship of c (bypass) to start-up time. input capacitor (c i ) the tpa6204a1 does not require input coupling capacitors if using a differential input source that is biased from 0.5 v to v dd ? 0.8 v. use 1% tolerance or better gain-setting resistors if not using input coupling capacitors. in the single-ended input application an input capacitor, c i , is required to allow the amplifier to bias the input signal to the proper dc level. in this case, c i and r i form a high-pass filter with the corner frequency determined in equation 2. f c 1 2 r i c i ?3 db f c the value of c i is important to consider as it directly af fects the bass (low frequency) performance of the circuit. consider the example where r i is 10 k ? and the specification calls for a flat bass response down to 100 hz. equation 2 is reconfigured as equation 3. c i 1 2 r i f c in this example, c i is 0.16 f, so one would likely choose a value in the range of 0.22 f to 0.47 f. ceramic capacitors sh ould be used when possible, as they are the best choice in preventing leakage current. when polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications, as the dc level there is held at v dd /2, which is likely higher than the source dc level. it is important to confirm the capacitor polarity in the application. decoupling capacitor (c s ) the tpa6204a1 is a high-performance cmos audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (thd) is as low as possible. power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. for higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series- resistance (esr) ceramic capacitor, typically 0.1 f to 1 f, placed as close as possible to the device v dd lead works best. for filtering lower frequency noise signals, a 10- f or greater capacitor placed near the audio power amplifier also helps, but is not required in most applications because of the high psrr of this device. (1) (2) (3)
slos429 ? may 2004 www.ti.com 11 fully differential amplifier efficiency and thermal information class-ab amplifiers are inefficient. the primary cause of these inefficiencies is voltage drop across the output stage transistors. there are two components of the internal voltage drop. one is the headroom or dc voltage drop that varies inversely to output power. the second component is due to the sinewave nature of the output. the total voltage drop can be calculated by subtracting the rms value of the output voltage from v dd . the internal voltage drop multiplied by the average value of the supply current, i dd (avg), determines the internal power dissipation of the amplifier. an easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power supply to the power delivered to the load. to accurately calculate the rms and average values of power in the load and in the amplifier, the current and voltage waveform shapes must first be understood (see figure 18). v (lrms) v o i dd i dd(avg) figure 18. voltage and current waveforms for btl amplifiers although the voltages and currents for se and btl are sinusoidal in the load, currents from the supply are different between se and btl configurations. in an se application the current waveform is a half-wave rectified shape, whereas in btl it is a full-wave rectified waveform. this means rms conversion factors are different. keep in mind that for most of the waveform both the push and pull transistors are not on at the same time, which supports the fact that each amplifier in the btl device only draws current from the supply for half the waveform. the following equations are the basis for calculating amplifier efficiency. efficiency of a btl amplifier p l p sup where: p l v l rms 2 r l , and v lrms v p 2 , therefore, p l v p 2 2r l p l = power delivered to load p sup = power drawn from power supply v lrms = rms voltage on btl load r l = load resistance v p = peak voltage on btl load i dd avg = average current drawn from the power supply v dd = power supply voltage btl = efficiency of a btl amplifier and p sup v dd i dd avg and i dd avg 1 0 v p r l sin(t) dt 1 v p r l [ cos(t) ] 0 2v p r l therefore, p sup 2v dd v p r l substituting p l and p sup into equation 6, efficiency of a btl amplifier v p 2 2r l 2v dd v p r l v p 4v dd v p 2p l r l where: btl 2p l r l 4v dd therefore, (4) (5)
slos429 ? may 2004 www.ti.com 12 table 2 and table 3 employ equation (5) to calculate efficiencies for four dif ferent output power levels. note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissipation over the normal operating range. note that the internal dissipation at full output power is less than in the half power range. calculating the efficiency for a specific system is the key to proper power supply design. for a 1-w audio system with 8- ? loads and a 5-v supply, the maximum draw on the power supply is almost 1.6 w. a final point to remember about class-ab amplifiers is how to manipulate the terms in the efficiency equation to the utmost advantage when possible. a simple formula for calculating the maximum power dissipated, p dmax , may be used for a differential output application: p dmax 2v 2 dd 2 r l p dmax for a 5-v, 8- ? system is 0.64 w. the maximum ambient temperature depends on the heat sinking ability of the pcb system. the derating factor for the 3 mm x 3 mm drb package is shown in the dissipation rating table. converting this to ja : ja 1 derating factor 1 0.0218 45.9 c w given ja , the maximum allowable junction temperature, and the maximum internal dissipation, the maximum ambient temperature can be calculated with the following equation. the maximum recommended junction temperature for the tpa6204a1 is 150 c. t a max t j max ja p dmax 150 45.9 ( 0.64 ) 120.6 c equation (8) shows that the maximum ambient temperature is 120.6 c (package limited to 85 c) at maximum power dissipation with a 5-v supply. table 2 shows that for most applications no airflow is required to keep junction temperatures in the specified range. the tpa6204a1 is designed with thermal protection that turns the device off when the junction temperature surpasses 150 c to prevent damage to the ic. in addition, using speakers with an impedance higher than 8- ? dramatically increases the thermal performance by reducing the output current. table 2. efficiency and maximum ambient temperature vs output power in 3.6-v 8- ? btl systems output power (w) efficiency (%) internal dissipation (w) power from supply (w) max ambient temperature (2) ( c) 0.1 27.6 0.262 0.36 85 0.2 39.0 0.312 0.51 85 0.5 61.7 0.310 0.81 85 0.6 67.6 0.288 0.89 85 (1) drb package (2) package limited to 85 c ambient table 3. efficiency and maximum ambient temperature vs output power in 5-v 8- ? systems output power (w) efficiency (%) internal dissipation (w) power from supply (w) max ambient t emperature (2) ( c) 0.5 44.4 0.625 1.13 85 1 62.8 0.592 1.60 85 1.36 73.3 0.496 1.86 85 1.7 81.9 0.375 2.08 85 (1) drb package (2) package limited to 85 c ambient (6) (7) (8)
slos429 ? may 2004 www.ti.com 13 pcb layout it is important to keep the tpa6204a1 external components very close to the tpa6204a1 to limit noise pickup. 8-pin qfn (drb) layout use the following land pattern for board layout with the 8-pin qfn (drb) package. note that the solder paste should use a hatch pattern to fill solder paste at 50% to ensure that there is not too much solder paste under the package. 0.65 mm 0.38 mm solder mask: 1.4 mm x 1.85 mm centered in package 0.7 mm 1.4 mm make solder paste a hatch pattern to fill 50% 3.3 mm 1.95 mm 0.33 mm plugged vias (5 places) figure 19. tpa6204a1 8-pin qfn (drb) board layout (top view)
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) tpa6204a1drb active son drb 8 121 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tpa6204a1drbg4 active son drb 8 121 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tpa6204a1drbr active son drb 8 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year tpa6204a1drbrg4 active son drb 8 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 6-dec-2006 addendum-page 1

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